Codee is a software development platform that provides tools to help improve the performance of C/C++/Fortran applications targeting multicore CPUs and GPUs. Codee Static Code Analyzer provides a systematic predictable approach to enforce C/C++/Fortran performance optimization best practices for the target environment: hardware, compiler and operating system. It also provides innovative Coding Assistant capabilities to enable semi-automatic source code rewriting through the software development lifecycle. Codee provides integrations with IDEs and CI/CD frameworks to make it possible to Shift Left Performance.
The OPTIMA partner, Codee, leveraged the Open Catalog of Best Practices for Performance (www.codee.com/catalog/) for FPGA programming, proposing new FPGA coding rules extracted from the OPTIMA guidelines in cooperation with Maxeler and ICCS, targeting the Maxeler and Xilinx programming environments, respectively.
FPGA (Field-Programmable Gate Array) development can be a complex and demanding field, requiring deep expertise and precision to harness the full potential of these powerful devices. With the inclusion of these groundbreaking coding rules in the catalog, we aim to empower FPGA developers by providing them with tested and proven strategies to optimize their designs, ultimately resulting in more efficient and high-performance FPGA applications.
The ‘OPTIMA catalog’ is now accessible at https://optima-hpc.eu/catalog/ with the following rules:
- OPTIMA001: Consider applying offloading parallelism to forall loop using Maxeler
- OPTIMA002: Consider applying offloading parallelism to scalar reduction loop using Maxeler
- OPTIMA003: Consider applying offloading parallelism to sparse reduction loop using Maxeler
- OPTIMA004: Consider applying loop unrolling to scalar reduction with non-associative operator using Maxeler
- OPTIMA005: Consider applying offloading parallelism to forall loop using Xilinx
- OPTIMA006: Consider applying offloading parallelism to scalar reduction loop using Xilinx
The ‘OPTIMA catalog’ demonstrates that the benefits of the Open Catalog of Best Practices for Performance are also beneficial in the scope of FPGA programming, beyond multicore CPU and GPU programming. It constitutes a valuable resource to leverage the knowledge gained in the OPTIMA project to the community of FPGA developers targeting FPGA-based HPC systems.
